COURSE UNIT TITLE

: FUNDAMENTALS OF VLSI DESIGN

Description of Individual Course Units

Course Unit Code Course Unit Title Type Of Course D U L ECTS
EED 4020 FUNDAMENTALS OF VLSI DESIGN ELECTIVE 3 2 0 6

Offered By

Electrical and Electronics Engineering

Level of Course Unit

First Cycle Programmes (Bachelor's Degree)

Course Coordinator

PROFESSOR UĞUR ÇAM

Offered to

Electrical and Electronics Engineering

Course Objective

This course covers basic principles of very large scale integration (VLSI). It begins with an overview of semiconductor materials. After this introduction, physical implementation of electronics devices (dioe, bipolar junction transistor, MOSFET) will be introduced. It continues with integrated circuit (IC) design processes. Then, analog integrated circuit layout wil be examined. Finally, the design of CMOS digital integrated circuits will be presented. In the design of digital ICs, HDL will be used.

Learning Outcomes of the Course Unit

1   Design of Semiconductor Devices
2   IC fabrication technologies
3   CMOS IC design
4   Hardware Description Languages (HDL)
5   Digital IC design with HDLs
6   FPGA Based Design

Mode of Delivery

Face -to- Face

Prerequisites and Co-requisites

None

Recomended Optional Programme Components

None

Course Contents

Week Subject Description
1 Introduction
2 Semiconductor Materials
3 Physical operation of electronics devices
4 Integrated circuits design processes
5 Analog integrated circuit design
6 Digital integrated circuit design
7 Hardware description languages (HDLs)
8 Midterm
9 Hardware description languages (HDLs)
10 FPGA based design
11 Project design
12 Project design
13 Project design
14 Summary and Discussion

Recomended or Required Reading

Textbook:K. Eshraghian, N. Weste: CMOS VLSI design, Addison-Wesley Publishing, Third Edition, 2004.
Additional textbook:: Baker R. J., Li H. W. and Boyce D. E.: CMOS Circuit Design, Layout, and Simulation, Chap. 7, USA, IEEE Press, 1998.

Planned Learning Activities and Teaching Methods

Lecture+Laboratory+Project

Assessment Methods

SORTING NUMBER SHORT CODE LONG CODE FORMULA
1 MTE MIDTERM EXAM
2 LAB LABORATORY
3 FIN FINAL EXAM
4 FCG FINAL COURSE GRADE MTE * 0.30 + LAB * 0.20 + FIN * 0.50
5 RST RESIT
6 FCGR FINAL COURSE GRADE (RESIT) MTE * 0.30 + LAB * 0.20 + RST * 0.50

Further Notes About Assessment Methods

None

Assessment Criteria

1,2,3,4,5 numbered course outcomes are evaulated by exams and projects.

Language of Instruction

English

Course Policies and Rules

%70 attendance for lectures and %80 attendance for laboratory are mandatory.

Contact Details for the Lecturer(s)



Prof. Dr. Ugur Cam
Dokuz Eylül University
Engineering Faculty
Electrical and Electronics Engineering
Tinaztepe, Buca, 35160, Izmir, Turkey
Phone: +90 232 3017197
Fax : +90 232 4534279
e-mail: ugur.cam@eee.deu.edu.tr
e-mail: ugur_cam@yahoo.com
http://www.eee.deu.edu.tr/~ucam

Office Hours

-

Work Placement(s)

None

Workload Calculation

Activities Number Time (hours) Total Work Load (hours)
Lectures 2 14 28
Lectures 3 14 42
Preparation for midterm exam 1 10 10
Design Project 1 10 10
Preparation for final exam 1 10 10
Preparations before/after weekly labs (6 lab woks) 6 5 30
Preparations before/after weekly lectures 14 1 14
Midterm 1 2 2
Final 1 2 2
TOTAL WORKLOAD (hours) 148

Contribution of Learning Outcomes to Programme Outcomes

PO/LOPO.1PO.2PO.3PO.4PO.5PO.6PO.7PO.8PO.9PO.10PO.11PO.12PO.13
LO.13
LO.234
LO.34
LO.445
LO.5425
LO.6