COURSE UNIT TITLE

: ADVANCED LOGIC DESIGN

DEGREE PROGRAMMES

Description of Individual Course Units

Course Unit Code Course Unit Title Type Of Course D U L ECTS
EED 4021 ADVANCED LOGIC DESIGN ELECTIVE 3 2 0 6

Offered By

Electrical and Electronics Engineering

Level of Course Unit

First Cycle Programmes (Bachelor's Degree)

Course Coordinator

ASISTANT PROFESSOR AHMET ÖZKURT

Offered to

Electrical and Electronics Engineering

Course Objective

The aim of the course is to present advanced logic design and implementation techniques that could be applied on Programmable Logic Devices (PLD) and Field Programmeble Gate Arrays (FPGA). Verilog Hardware desicription Language will be introduced and advanced logic simulation tehniques will be presented.

Learning Outcomes of the Course Unit

1   to be able to design synchronous and asynchronous digital circuits using Verilog hardware description language
2   to be able to simulate advanced digital circuit designs on state of the art FPGA simulators and draw conclusions from the results.
3   To be able to optimize and implement advanced digital circuit designs on PLD and FPGA devices using Electronic Design Automation(EDA) tools.
4   To be able to use Logic Analyzers to validate a logic design.

Mode of Delivery

Face -to- Face

Prerequisites and Co-requisites

EED 3008 - MICROPROCESSOR SYSTEMS
EED 3018 - MICROPROCESSOR SYSTEMS

Recomended Optional Programme Components

None

Course Contents

Week Subject Description
1 Course Outline, Review of logical design methods, introduction to Verilog
2 Implementation Technologies, Programmable Logic gates, Optimized implementation of logic functions
3 Verilog data types and operators, modules and ports, gate level modeling, time simulation Lab: Presentation of CPLD/FPGA Boards
4 Verilog Behavioral models, number representations and aricmetic circuits, aricmetic operations, Project Assignment,
5 Verilog specifications of combinational circuits, Lab: Introduction to Logic Analyzers
6 Combinational logic building blocks, encoders/decoders, arithmetic comparison, etc
7 Review
8 Midterm
9 Verilog and the basic latch, gated SR and D latch, master-slave and edge-triggered flip flops, counters, shift registers
10 Verilog Synchronous sequential circuits, design process, state assignment,
11 Mealy & Moore machines, finite state machine design, state minimization
12 Finite state machine design examples, Verilog representations
13 Microprocessor based design practices, hardware and software IP cores
14 Project

Recomended or Required Reading

Reference 1Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design,
McGraw-Hill Higher Education, 2003, ISBN 0-07-283878-7
Reference2 : Samir Palnitkar, Verilog HDL, 2nd Edition, Prentice Hall, 2003, ISBN 0-13-044911-3
Other: Lecture notes

Planned Learning Activities and Teaching Methods

Lectures with active discussions, midterm and final examinations, laboratory sessions with active discussions, a term long team project.

Assessment Methods

SORTING NUMBER SHORT CODE LONG CODE FORMULA
1 MTE MIDTERM EXAM
2 ASG ASSIGNMENT
3 PRC PRACTICE
4 FIN FINAL EXAM
5 FCG FINAL COURSE GRADE MTE * 0.20 + ASG * 0.20 + PRC * 0.10 + FIN * 0.50
6 RST RESIT
7 FCG FINAL COURSE GRADE MTE * 0.20 + ASG * 0.20 + PRC * 0.10 + RST * 0.50

Further Notes About Assessment Methods

None

Assessment Criteria

Students ability to design digital circutary in course outcomes are evaluated using 1 midterm and 1 final examination. Their ability to use the information and capture the concepts in applications are evaluated in laboratory experiments for which they have to prepare technical reports. Their abilitiy to bind the knowledge for design and implementation is to be evaluated by a team project. Midterm consist 15%, Team homeworkt 15%, Laboratory assignments 20% and final examination consists 50% of the final grade.

Language of Instruction

English

Course Policies and Rules

To be announced.

Contact Details for the Lecturer(s)

ahmet Ozkurt
ahmet.ozkur@deu.edu.tr
Te: 3017134

Office Hours

2 hours per week

Work Placement(s)

None

Workload Calculation

Activities Number Time (hours) Total Work Load (hours)
Lectures 14 3 42
Tutorials 5 2 10
Preparations before/after weekly lectures 14 4 56
Preparing assignments 10 2 20
Preparation for midterm exam 1 8 8
Preparation for final exam 1 8 8
Final 1 3 3
Midterm 1 2 2
TOTAL WORKLOAD (hours) 149

Contribution of Learning Outcomes to Programme Outcomes

PO/LOPO.1PO.2PO.3PO.4PO.5PO.6PO.7PO.8PO.9PO.10PO.11PO.12PO.13
LO.155532323
LO.255535223
LO.355535223
LO.45553523

CONTACT INFORMATION
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Phone: +90(232) 412 12 12 - Fax: +90 (232) 464 81 35

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